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Card #c526IR // #c526Synthesis

Six interrupts live at fixed ROM addresses — Reset 0000H, INT0 0003H, TF0 000BH, INT1 0013H, TF1 001BH, serial 0023H. On an interrupt the CPU finishes the current instruction, pushes the PC, and jumps; the ISR ends with RETI, which restores the PC and clears the interrupt-in-service flag so the pin can fire again. The IE register masks each interrupt individually but nothing works unless EA (IE.7) is set, and the IP register can reorder the default priority (INT0, TF0, INT1, TF1, serial).

— In our words · Source: 8051 Microcontroller Notes

[Use when]

Designing interrupt-driven 8051 firmware — set EA plus the individual IE bit, place the ISR at its vector address, and end with RETI (never RET) so the interrupt can re-arm.

[Why it matters]

The notes' core contrast is polling versus interrupts — polling burns the CPU watching devices that need nothing, while interrupts let the chip do real work until TF or a pin demands attention — and the whole system hinges on two one-bit disciplines: EA as the master switch and RETI's hidden flag-clear.

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